A static random access memory (SRAM) bitcell includes a pair of cross-coupled inverters. Each cross-coupled inverter includes a PMOS transistor that can charge a true (Q) data node or complement (QB) data node. The Q node couples through an NMOS access transistor to the a bit line whereas the QBdata node couples through another NMOS access transistor to a complement bit line. During a write operation in which the binary content of the bitcell is changed, one of the PMOS transistors will initially be on and charging its data node while the corresponding access transistor is attempting to discharge the same node through the corresponding bit or complement bit line. The NMOS access transistor must thus be relatively strong with regard to the corresponding PMOS transistor in the inverter so that the data node can be discharged relatively quickly despite the struggle with the PMOS transistor. To strengthen the NMOS access transistor, it is conventional to provide a negative voltage on the corresponding bit line instead of just grounding this bit line during the write operation. This negative voltage increases the strength of the NMOS access transistor in comparison to the inverter PMOS transistor so that the NMOS access transistor can quickly discharge the corresponding data node.
A coupling capacitor is conventionally used to provide the negative voltage to the bit line. This can be problematic in that the negative boost to the bit line is dependent upon not only the coupling capacitance but also the bit line capacitance, which will vary depending upon the number of bit cells in a given memory configuration and process corner. Depending upon the memory configuration and process corner, the negative boost may be too small, resulting in write failure. Conversely, the negative boost may be too large, resulting in device damage.
Accordingly, there is a need in the art for improved negative bit line assist architectures.